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hufa76413d k8t _f085 n-channel log i c level ultrafet ? power m o sfet 60v, 4.8a, 56m ? ge nera l description th ese n- channel power mosfets are manufactured us- ing the innovative ultrafet ? pr ocess . this advanced pro- cess technology achieves the lowest possible on- resistance per silicon area, resulting in outstanding perfor- mance. this device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low re- verse recovery time and stored charge. it was designed for use in applications where power efficiency is important, such as switching regulators, switching convertors, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and battery-operated products. applicat ions ? mot or and load control ? powertrain management feat u res ? 150c m a ximum junction temperature ? uis capability (single pulse and repetitive pulse) ? ultra-low on-resistance r ds(o n) = 0. 049 ?, v gs = 10v ? ult ra-low on-resistance r ds( o n) = 0.056 ?, v gs = 5v mosfet maxi mum ratings t a = 25c unless ot herwise noted thermal cha racteristics this p roduct has been designed to meet the extreme test conditions and environment demanded by the automotive industry. for a copy of the requirements, see aec q101 at: http://www.aecouncil.com/ reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.htm l. all fairchild semiconductor products are manufactured, assembled and tested under iso9000 and qs9000 quality systems certification. symbol p a rameter ratings units v dss drain t o s ource voltage 60 v v gs gate to source voltage 16 v i d drain cur r ent 5.1 a continuous (t c = 25 o c, v gs = 10v) c ontinuous (t c = 25 o c, v gs = 5v) 4 .8 a c ontinuous (t c = 125 o c, v gs = 5v, r ja = 228 o c/w) 1 a pu l sed figure 4 a e as single p u lse avalanche energy (note 1) 260 mj p d power dissip a tion 2.5 w derate above 25 o c0 . 0 2 w / o c t j , t stg operat ing and storage temperature -55 to 150 o c r ja therma l res istance junction to ambient so-8 (note 2) 50 o c/w r ja therma l res istance junction to ambient so-8 (note 3) 191 o c/w r ja therma l res istance junction to ambient so-8 (note 4) 228 o c/w g1 (2) d1 (8 ) s1 (1) d1 (7) d2 (6) d2 (5) s2 (3) g2 (4) so-8 huf a76413dk8t_f085 n-channel logic level ultrafet power mosfet ? ? qualified to aec q101 ? rohs compliant october 2010 ? 2010 f a irchild semiconductor corporation hufa76413dk8t _f085 rev. c1 www.fairchildsemi.com 1
package marking and ordering information electrical characteristics t a = 25c unl es s otherwise noted of f characteristics on characteristics dynamic characteristics switching characteristics (v gs = 5v ) dra i n-source diode characteristics notes: 1: starting t j = 25c , l = 20mh, i as = 5.1 a 2: r ja is 50 o c/w when mounted on a 0.5 in 2 copper pa d on fr-4 at 1 second. 3: r ja is 191 o c/w when mounted on a 0.027 in 2 copper pad on f r-4 at 1000 seconds. 4: r ja is 228 o c/w when mounted on a 0.006 in 2 copper pad on f r-4 at 1000 seconds. devi ce m arking device package reel size tape width quantity 76413dk8 hufa76413dk8t_f085 so-8 330mm 12mm 2500 units symbol parameter test conditions min typ max units b vdss drain t o sourc e breakdown voltage i d = 250 a, v gs = 0v 60 - - v i dss ze ro g ate voltage drain current v ds = 50v - - 1 a v gs = 0v t a = 150 o c - - 250 i gss gat e to source leakage current v gs = 16v - - 100 na v gs( t h) ga t e to source threshold voltage v gs = v ds , i d = 25 0 a1 -3v r ds( o n) drain to sourc e on resistance i d = 5.1a , v gs = 10v - 0.041 0.049 ? i d = 4. 8a , v gs = 5v - 0.048 0.056 i d = 4. 8a , v gs = 5v t a = 150 o c - 0.091 0.106 c iss inpu t capacitance v ds = 25v , v gs = 0v , f = 1mhz - 620 - pf c oss out put capacitance - 180 - pf c rss revers e t ransfer capacitance - 30 - pf q g(to t ) tot al g ate charge at 10v v gs = 0v t o 10v v dd = 30v i d = 4. 8a i g = 1. 0ma 18 23 nc q g(5) tot al g ate charge at 5v v gs = 0 v to 5v - 10 13 nc q g(th ) th reshold g ate charge v gs = 0v t o 1v - 0.6 0.8 nc q gs gat e to source gate charge - 1.8 - nc q gd gate to drain ?miller? charge - 5 - nc t on tur n -on time v dd = 30v , i d = 1a v gs = 5 v , r gs = 16 ? - - 44 ns t d(on ) turn- on delay time - 10 - ns t r rise ti me - 19 - ns t d(of f ) tu r n-off delay time - 45 - ns t f fal l time - 27 - ns t off tu r n-off time - - 108 ns v sd source t o drain diode voltage i sd = 4.8a - - 1.25 v i sd = 2. 4a - - 1.0 v t rr re ver se recovery time i sd = 4. 8a, di sd /dt = 100a/ s- - 43 ns q rr revers e r ecovered charge i sd = 4. 8a, di sd /dt = 100a/ s- - 55 nc hufa76413dk8t _f085 n-channel logic level ultrafet power mosfet ? hufa76413dk8t _f085 rev . c1 www.fairchildsemi.com 2
typica l characteristics t a = 25c unl ess otherwise noted figu re 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t a , am bient temperature ( o c) po wer dissipation multiplier 0 0 2 5 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 0 2 4 6 25 50 75 100 125 150 -i d , d rain current (a) t a , case temperature ( o c) v gs = 10v , r ja =50 o c/w v gs = 5v , r ja =22 8 o c/w 0.00 1 0.01 0.1 1 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 4 10 -5 t, rectangular pulse duration (s) z ja , norm alized thermal impedance note s: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a p dm t 1 t 2 0.5 0. 2 0.1 0.05 0.01 0.02 duty cycle - descending order sin gle pulse v gs = 10v r ja =50 o c/w 10 100 300 2 10 -5 10 -3 10 -4 10 -2 10 -1 10 0 10 1 10 2 10 3 i dm , peak current (a) t, pulse width (s) transconduct ance may limit current in this region v gs = 5v t a = 25 o c i = i 25 175 - t a 150 for t emperatures above 25 o c de rate peak current as f ollows: v gs = 1 0v r ja =50 o c/w huf a76413dk8t _f085 n-channel logic level ultrafet power mosfet ? hufa7641 3 dk8t _f085 rev . c1 www.fairchildsemi.com 3
figu re 5. forward bias safe operating area figure 6. unclamped inductive switching capability figure 7. transfer characteristics figure 8. saturation characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature typica l characteristics t a = 25c unl ess otherwise noted 1 10 100 11 0 1 0 0 0.2 200 v ds , drai n to source voltage (v) i d , drain current ( a) t j = ma x rated t a = 25 o c sin gle pulse lim ited by r ds( on) area m ay be operation in this 100 s 10ms 1ms 1 10 0.1 1 1 0 15 40 i as , av alanche current (a) t av , ti me in avalanche (ms) start ing t j = 25 o c st arting t j = 15 0 o c t av = (l )(i as )/(1 .3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r) /(1.3*rated bv dss - v dd ) +1 ] 0 5 10 15 20 25 1.5 2.0 2.5 3.0 3.5 4.0 i d , drain current (a) v gs , gat e to source voltage (v) pulse du ration = 80 s duty cycle = 0.5% max v dd = 15v t j = 1 50 o c t j = 25 o c t j = -5 5 o c 0 5 10 15 20 25 0 0 .5 1.0 1.5 2.0 i d , drain current (a) v ds , d rain to source voltage (v) v gs = 3. 5v pu lse duration = 80 s duty cycle = 0.5% max v gs = 3 v t a = 25 o c v gs = 5 v v gs = 1 0v 40 50 60 70 80 90 100 24681 0 i d = 1a v gs , gat e to source voltage (v) i d = 5. 1a r ds( on) , drain to source on resistance (m ? ) puls e duration = 80 s duty cycle = 0.5% max 0.5 1.0 1.5 2.0 -80 -40 0 40 80 120 160 normal ized drain to source t j , junc tion temperature ( o c) on resistance v gs = 10 v, i d =5 .1a pul se duration = 80 s duty cycle = 0.5% max huf a76413dk8t _f085 n-channel logic level ultrafet power mosfet ? hufa7641 3 dk8t _f085 rev . c1 www.fairchildsemi.com 4
fi gur e 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage figure 14. gate charge waveforms for constant gate currents figure 15. switching time vs gate resistance typica l characteristics t a = 25c unl ess otherwise noted 0.6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 normal ized gate t j , ju nction temperature ( o c) v gs = v ds , i d = 25 0 a thresh old voltage 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 160 t j , junct ion temperature ( o c) norma lized drain to source i d = 25 0 a breakdown vol tage 10 100 1 000 0.1 1 10 60 2000 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v , f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 2 4 6 8 10 0 5 1 0 15 20 v gs , gat e to source voltage (v) q g , ga te charge (nc) v dd = 30v i d = 4. 8a i d = 1a w aveforms in descending order: 0 50 100 150 0 1 020304050 s w itching time (ns) r gs , ga te to source resistance ( ? ) v gs = 5v , v dd = 3 0v, i d = 1 a t d( o ff) t r t d( on ) t f huf a76413dk8t _f085 n-channel logic level ultrafet power mosfet ? hufa7641 3 dk8t _f085 rev . c1 www.fairchildsemi.com 5
test circuits and waveforms figure 16 . unclamped energy test circuit figure 17. unclamped energy waveforms figure 18. gate charge test circuit figure 19. gate charge waveforms figure 20. switching time test circuit figure 21. switching time waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut var y t p to o btain required peak i as 0v v dd v ds bv dss t p i as t av 0 r l v gs + - v ds v dd dut i g(re f) v dd q g(th ) v gs = 1v q g(5 ) v gs = 5v q g( tot) v gs = 10 v v ds v gs i g(re f) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(o n) t r 90% 10% v ds 90% 10% t f t d(o ff) t off 90% 50% 50% 10 % pulse width v gs 0 0 huf a76413dk8t _f085 n-channel logic level ultrafet power mosfet ? hufa7641 3 dk8t _f085 rev . c1 www.fairchildsemi.com 6
thermal resistance vs. mounting pad area t h e maximum rated junction temperature, t jm , and t he thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in a n application. therefore the application?s ambient temperature, t a ( o c), and t hermal resistance r ja ( o c/w ) mus t be reviewed to ensure that t jm is never ex ceeded. equat ion 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. in using surface mount devices such as the so-8 package, the environment in which it is applied will have a significant influence on the part?s current and maximum power dissipation ratings. precise determination of p dm is c omplex and influenced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air flow and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the designer?s preliminary application evaluation. figure 22 defines the r ja f or t he device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. thermal resistances corresponding to other copper areas can be obtained from figure 22 or by calculation using equation 2. the area, in square inches is the top copper area including the gate and source pads. the dual die so-8 package introduces an additional thermal coupling resistance, r b. equat i on 3 describes r b as a f unction of the top copper mouting pad area. the thermal coupling resistance vs. copper area is also graphically depicted in figure 22. (eq . 1) p dm t jm t a ? () r ja --- --- ----------------------- = (eq . 2) r ja 10 3. 2 24.3 area () ln ? = (eq . 3) r b 46 . 4 21.7 area () ln ? = figu r e 22. thermal resistance vs mounting pad area 0 50 100 150 200 250 300 0.001 0. 01 0.1 1 r ? , r ja ( o c/w) area , top copper area (in 2 ) pe r die 191 o c/ w - 0.027in 2 228 o c/ w - 0.006in 2 r ja = 103. 2 - 24.3 * ln (ar ea) r ? = 46. 4 - 21.7 * ln (ar ea) huf a76413dk8t _f085 n-channel logic level ultrafet power mosfet ? hufa7641 3 dk8t _f085 rev . c1 www.fairchildsemi.com 7
pspic e electrical model . s ubckt hufa76413dk8t 2 1 3 ; rev april 2002 ca 12 8 7.8e-10 cb 15 14 9.8e-10 cin 6 8 5.8e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 67.4 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 1.34e-9 lsource 3 7 0.59e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 22.5e-3 rgate 9 20 2.2 rldrain 2 5 10 rlgate 1 9 13.4 rlsource 3 7 5.9 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 15.3e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*180),2.5))} .model dbodymod d (is = 8e-13 rs = 1.58e-2 trs1 = 1e-3 trs2 = 3e-6 xti=3.2 cjo = 8e-10 tt = 3.2e-8 m = 0.54) .model dbreakmod d (rs = 1.18 trs1 = 2e-3 trs2 = -2.6e-5) .model dplcapmod d (cjo = 5.7e-10 is = 1e-30 n = 10 m = 0.87) .model mmedmod nmos (vto = 1.68 kp = 2 is =1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 2.2) .model mstromod nmos (vto = 2.05 kp =35 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.48 kp = 0.04 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 22 rs = 0.1) .model rbreakmod res (tc1 = 1.15e-3 tc2 = -7.5e-7) .model rdrainmod res (tc1 = 8.5e-3 tc2 = 1.2e-5) .model rslcmod res (tc1 = 3e-2 tc2 = 5.3e-7) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = -1.4e-3 tc2 = -7e-6) .model rvtempmod res (tc1 = -1.5e-3 tc2 = 2e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -5.0 voff= -1.0) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -1.0 voff= -5.0) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.2 voff= 0.2) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.2 voff= -0.2) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvt emp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mwe ak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc 2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 huf a76413dk8t _f085 n-channel logic level ultrafet power mosfet ? hufa7641 3 dk8t _f085 rev . c1 www.fairchildsemi.com 8
saber electrical model re v april 2002 template hufa76413dk8t n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 8e-13, rs = 1.58e-2, trs1 = 1e-3, trs2 = 3e-6, xti = 3.2, cjo = 8e-10, tt = 3.2e-8, m = 0.54) dp..model dbreakmod = (rs = 1.18, trs1 = 2e-3, trs2 = -2.6e-5) dp..model dplcapmod = (cjo = 5.7e-10, isl =10e-30, nl =10, m = 0.87) m..model mmedmod = (type=_n, vto = 1.68, kp = 2, is =1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.05, kp = 35, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.48, kp = 0.04, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.0, voff = -1.0) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.0, voff = -5.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.2, voff = 0.2) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.2) c.ca n12 n8 = 7.8e-10 c.cb n15 n14 = 9.8e-10 c.cin n6 n8 = 5.8e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1.34e-9 l.lsource n3 n7 = 0.59e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.15e-3, tc2 = -7.5e-7 res.rdrain n50 n16 = 22.5e-3, tc1 = 8.5e-3, tc2 = 1.2e-5 res.rgate n9 n20 = 2.2 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 13.4 res.rlsource n3 n7 = 5.9 res.rslc1 n5 n51= 1e-6, tc1 = 3e-2, tc2 =5.3e-7 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 15.3e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 2e-7 res.rvthres n22 n8 = 1, tc1 = -1.4e-3, tc2 = -7e-6 spe.ebreak n11 n7 n17 n18 = 67.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2.5)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rv temp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mwe ak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rsl c2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 huf a76413dk8t _f085 n-channel logic level ultrafet power mosfet ? hufa7641 3 dk8t _f085 rev . c1 www.fairchildsemi.com 9
sp ice thermal model re v april 2002 hufa76413dk8t copper area = 0.493in 2 ct he rm1 th 8 8.5e-4 ctherm2 8 7 1.8e-3 ctherm3 7 6 5.0e-3 ctherm4 6 5 1.3e-2 ctherm5 5 4 4.0e-2 ctherm6 4 3 1.5e-1 ctherm7 3 2 7.5e-1 ctherm8 2 tl 3 rtherm1 th 8 3.5e-2 rtherm2 8 7 6.0e-1 rtherm3 7 6 2 rtherm4 6 5 8 rtherm5 5 4 18 rtherm6 4 3 20 rtherm7 3 2 23 rtherm8 2 tl 25 sa ber thermal model s a ber thermal model hufa76413dk8t copper area = 0.493in 2 tem plate thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =8.5e-4 ctherm.ctherm2 8 7 =1.8e-3 ctherm.ctherm3 7 6 =5.0e-3 ctherm.ctherm4 6 5 =1.3e-2 ctherm.ctherm5 5 4 =4.0e-2 ctherm.ctherm6 4 3 =1.5e-1 ctherm.ctherm7 3 2 =7.5e-1 ctherm.ctherm8 2 tl =3 rtherm.rtherm1 th 8 =3.5e-2 rtherm.rtherm2 8 7 =6.0e-1 rtherm.rtherm3 7 6 =2 rtherm.rtherm4 6 5 =8 rtherm.rtherm5 5 4 =18 rtherm.rtherm6 4 3 =20 rtherm.rtherm7 3 2 =23 rtherm.rtherm8 2 tl =25 } rt herm 6 rtherm8 rtherm7 rtherm5 rtherm4 rtherm3 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 7 j unc tion case 8 th rt herm 2 rtherm1 ctherm7 ctherm8 huf a76413dk8t _f085 n-channel logic level ultrafet power mosfet ? hufa7641 3 dk8t _f085 rev . c1 www.fairchildsemi.com 10
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supersot ? -3 supersot ? -6 supersot ? -8 supremos ? syncfet ? sync-lock? ? * t he p ower franchise ? t i nyboost ? tinybuck ? tinycalc ? tinylogic ? ti n yopto ? tinypower ? tinypwm ? tinywire ? trifault detect ? truecurrent ? * serdes ? uhc ? u l tra frfet ? unifet ? vcx ? visualmax ? xs? * trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer f a irchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy f a irchild?s products are not authorized for use as critical co mponents in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provi ded in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. a n ti-counterfeiting policy fai r child semiconductor corporation's anti-counterfeiting policy. fairchild's anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support. counterfeiting of semiconductor parts is a growing problem in t he industry. all manufacturers of semiconductor products are exp eriencing counterfeiting of their parts. customers who inadvertently purchase counter feit parts experience many problems such as loss of brand reputation, substandard p erformance, failed applications, and increased cost of production and manufacturing delays. fairchild is taking strong measures to protect ourselves and our cus tomers from the proliferation of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts eit her directly from fairchild or from a uthorized fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or from authorized fairchi ld distributors are genuine parts, have full traceability, meet fairch ild's quality standards for handling and storage and pr ovide access to fair child's full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and will appropr iately address any warranty issues t hat may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from u nauthorized sources. fairchild is committed to combat this glo bal problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. product status definitions d e finition of terms datasheet identification product status definition a d vance information formative / in design datasheet contains the design s pecifications for product developmen t. specifications may change in any manner without notice. p r eliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. n o identification needed full production datasheet contains final specific ations. fairchild semiconductor reserves the right to make changes at any time without notice to improve the design. obsol e te not in production datasheet contains specificati ons on a product that is disconti nued by fairchild semiconductor. the datasheet is for reference information only. re v. i48 huf a76413dk8t _f085 n-channel logic level ultrafet power mosfet ? hufa7641 3 dk8t _f085 rev . c1 www.fairchildsemi.com 11

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